The present invention relates to a semiconductor device and, for example, relates to a semiconductor device having a plurality of data transfer blocks.
Conventionally, a DDR-PHY (Double Data Rate—PHYsical interface) as an interface between a memory controller and a DRAM (Dynamic Random Access Memory) is known (refer to, for example, non-patent literature 1).
The DDR-PHY converts parallel data from a memory controller to serial data, transmits the serial data to a DRAM, converts serial data received from the DRAM to parallel data, and transmits the parallel data to the memory controller.
In the DDR-PHY, there is a case that a clock skew becomes an issue. As a measure against the clock skew, for example, patent literature 1 describes a configuration that, at the time of transferring data between two circuit systems of different clocks, a signal latched by a clock A is latched again by a clock B.